So far has been conventionally employed a method of forming an electronic circuit by connecting an electronic component, examples of which include passive components such as a resistor and a capacitor or a functional component such as a semiconductor element, on a wiring substrate by means of the reflow soldering.
In the reflow soldering, a predetermined amount of soldering paste or the like is applied to given connecting terminals on the wiring substrate, and electrode terminals of the electronic component are then secured with an adhesive strength of the soldering paste so as to face the connecting terminals. After that, the wiring substrate to which the electronic component is adhered by the soldering paste is placed in a reflow furnace so that the solder is melted. As a result, the electrode terminals of the electronic component and the connecting terminals of the wiring substrate are connected to each other.
In the foregoing method, the wiring substrate and the electronic component are secured to each other with the adhesive strength of the soldering paste alone, and the two components are bonded to each other by a self-alignment effect resulting from the surface tension of the solder when the solder is melted so that displacement of any degree which might be generated between the connecting terminals and the electrode terminals can be resolved.
However, the following problem has arisen since a microchip component, a CSP package or a semiconductor element having the bare-chip structure is directly mounted so as to deal with a size and a thickness of the wiring substrate which is increasingly reduced in recent years. In the case where a thin electronic component such as a bare-chip semiconductor element is used on the wiring substrate, a heating process in the reflow generates warp or gurge, which results in the failure to obtain the self-alignment effect, and a part to be soldered unfavorably comes off and fails to be soldered. In the case where an electronic component having a micro size, such as a chip component having the 0603 size or a bare-chip semiconductor element which was polished to be thin, is used, these electronic components cannot be accurately placed at the connecting terminals by a wind pressure generated in the reflow furnace.
In order to solve the problem, there is available such a method that the solder is melted when the electronic component is pressurized and heated from a rear surface thereof by a heating/pressurizing head after the electrode terminals of the electronic component are adhered to the connecting terminals of the wiring substrate via the soldering paste, so that the electrode terminals and the connecting terminals are connected to each other. This method does not generate the displacement of the components described earlier. However, the self-alignment effect is not exerted, which makes it necessary to align the positions of the electrode terminals of the electronic component and the connecting terminals of the wiring substrate in advance with a high accuracy. It is further necessary to retain the electronic component and the wiring substrate, which were position-aligned, until the solder is melted and solidified.
In order to respond to the necessities, a method of mounting a semiconductor chip (hereinafter, referred to as first mounting method) designed to improve a positioning accuracy and a production efficiency in the surface mounting was proposed.
The first mounting method comprises steps of:                applying the soldering paste to a predetermined position on the wiring substrate and place the electronic component;        melting the soldering paste to finally reach at least a melting temperature and soldering leads of the electronic component to lands of the wiring substrate; and        vibrating the wiring substrate until any of lead-land connecting points is cooled down to finally reach a solidification point after the soldering paste is melted at all of the connecting points.        
(for example, see the Patent Document 1).
According to the first mounting method, the applied vibration reduces a frictional resistance between the electronic component and the wiring substrate. In the state where the frictional resistance is reduced, the leads and the lands to be soldered are attracted to each other by the surface tension generated in the melted solder so that a distance therebetween can be minimized. As a result, they can be favorably soldered to each other.
Further, a method of mounting a semiconductor chip on a wiring substrate via a solder bump (hereinafter, referred to as second mounting method) was proposed.
The second mounting method comprises steps of:                retaining the semiconductor chip in a bonding tool and align a position of the semiconductor chip with respect to the wiring substrate;        making the solder bump of the position-aligned semiconductor chip contact an electrode pad at a predetermined position on the wiring substrate;        heating and melting the solder bump;        adjusting an interval between the wiring substrate and the semiconductor chip during the melting process; and        correcting any displacement between the wiring substrate and the semiconductor chip after the melting process by driving the bonding tool in an XY θ direction using an self-alignment action of the melted solder bump.        
(for example, see the Patent Document 2)                Patent Document 1: H06-260744 of the Japanese Patent Publication Laid-Open        Patent Document 2: H10-032225 of the Japanese Patent Publication Laid-Open        